Complexity and Performance Tradeoffs with FPGA Partial Reconfiguration Interfaces

Two different interfaces, namely the JTAG and SelectMAP interfaces, have been proposed for controlling and managing partial reconfiguration of SRAM-based Field Programmable Gate Arrays (FGPAs). Each of these interfaces provides distinct advantages in terms of area overhead and reconfiguration latency. In this paper, two corresponding sets of Application Programming Interfaces (APIs) are developed to facilitate communication between a host machine and reconfigurable board. Based on several testing considerations, these APIs are evaluated to validate partial reconfiguration functionality and assess their relative performance. Experiments are conducted in order to assess the tradeoffs between design complexity and area overhead, reconfiguration flexibility, and reconfiguration latency. The results show that the SelectMAP interface is highly suitable when reconfiguration latency needs to be kept to a minimum at the expense of a large area overhead. On the other hand, the JTAG interface is preferable if significant control over the placement of reconfigurable modules in the reconfigurable fabric of the FPGA chip is desired. The JTAG design consumes a factor of 5 to 18 times fewer logic resources and a third of the device pins, but can incur reconfiguration latency up to 40 times longer than the SelectMAP design.